// Copyright (C) 1953-2022 NUDT
// Verilog module name - stream_forwarding_control 
// Version: V4.0.0.20220524
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         use RAM to cahce the forward table
//         parse ctrl data,and compelet the configuration of the lookup table 
//         time division multiplexing for receive md come from network port and host port
//         determine whether a table lookup is required
//         extract flow_id from md,and complete the table
//         forward based on the result of the lookup table
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module stream_forwarding_control
#(
    parameter NUM_GMAC = 8,  
    parameter NUM_XGMAC = 0	
)
(
        i_clk,               
        i_rst_n,
        
        i_cyclestart,
        iv_inject_period,
        
        i_pkt_rx_finish      ,
		//i_pkt_rx_finish_p0   ,
        //i_pkt_rx_finish_p1   ,
        //i_pkt_rx_finish_p2   ,
        //i_pkt_rx_finish_p3   ,
        //i_pkt_rx_finish_p4   ,
        //i_pkt_rx_finish_p5   ,
        //i_pkt_rx_finish_p6   ,
        //i_pkt_rx_finish_p7   ,
        //i_pkt_rx_finish_p8   ,
        //i_pkt_rx_finish_p9   ,
        //i_pkt_rx_finish_p10  ,
        //i_pkt_rx_finish_p11  ,
        //i_pkt_rx_finish_p12  ,
        //i_pkt_rx_finish_p13  ,
        //i_pkt_rx_finish_p14  ,
        //i_pkt_rx_finish_p15  ,
        //i_pkt_rx_finish_p16  ,
        //i_pkt_rx_finish_p17  ,
        //i_pkt_rx_finish_p18  ,
        //i_pkt_rx_finish_p19  ,
        //i_pkt_rx_finish_p20  ,
        //i_pkt_rx_finish_p21  ,
        //i_pkt_rx_finish_p22  ,
        //i_pkt_rx_finish_p23  ,
        //i_pkt_rx_finish_p24  ,
        //i_pkt_rx_finish_p25  ,
        //i_pkt_rx_finish_p26  ,
        //i_pkt_rx_finish_p27  ,
        //i_pkt_rx_finish_p28  ,
        //i_pkt_rx_finish_p29  ,
        //i_pkt_rx_finish_p30  ,
        //i_pkt_rx_finish_p31  ,
        //i_pkt_rx_finish_p32  ,
        
        iv_md_p0,
        i_md_wr_p0,
        o_md_ack_p0,
        
        iv_md_p1,
        i_md_wr_p1,
        o_md_ack_p1,
        
        iv_md_p2,
        i_md_wr_p2,
        o_md_ack_p2,
        
        iv_md_p3,
        i_md_wr_p3,
        o_md_ack_p3, 
        
        iv_md_p4,
        i_md_wr_p4,
        o_md_ack_p4,    
        
        iv_md_p5,
        i_md_wr_p5,
        o_md_ack_p5,    
        
        iv_md_p6,
        i_md_wr_p6,
        o_md_ack_p6,    
        
        iv_md_p7,
        i_md_wr_p7,
        o_md_ack_p7,    
        
        iv_md_p8,
        i_md_wr_p8,
        o_md_ack_p8,    
        
        iv_md_p9,
        i_md_wr_p9,
        o_md_ack_p9,    
        
        iv_md_p10,
        i_md_wr_p10,
        o_md_ack_p10,    
        
        iv_md_p11,
        i_md_wr_p11,
        o_md_ack_p11,    
        
        iv_md_p12,
        i_md_wr_p12,
        o_md_ack_p12,    
        
        iv_md_p13,
        i_md_wr_p13,
        o_md_ack_p13,    
        
        iv_md_p14,
        i_md_wr_p14,
        o_md_ack_p14,    
        
        iv_md_p15,
        i_md_wr_p15,
        o_md_ack_p15,    
        
        iv_md_p16,
        i_md_wr_p16,
        o_md_ack_p16,    
        
        iv_md_p17,
        i_md_wr_p17,
        o_md_ack_p17,    
        
        iv_md_p18,
        i_md_wr_p18,
        o_md_ack_p18,    
        
        iv_md_p19,
        i_md_wr_p19,
        o_md_ack_p19,    
        
        iv_md_p20,
        i_md_wr_p20,
        o_md_ack_p20,    
        
        iv_md_p21,
        i_md_wr_p21,
        o_md_ack_p21,    
        
        iv_md_p22,
        i_md_wr_p22,
        o_md_ack_p22,    
        
        iv_md_p23,
        i_md_wr_p23,
        o_md_ack_p23,    
        
        iv_md_p24,
        i_md_wr_p24,
        o_md_ack_p24,    
        
        iv_md_p25,
        i_md_wr_p25,
        o_md_ack_p25,    
        
        iv_md_p26,
        i_md_wr_p26,
        o_md_ack_p26,    
        
        iv_md_p27,
        i_md_wr_p27,
        o_md_ack_p27,    
        
        iv_md_p28,
        i_md_wr_p28,
        o_md_ack_p28,    
        
        iv_md_p29,
        i_md_wr_p29,
        o_md_ack_p29,    
        
        iv_md_p30,
        i_md_wr_p30,
        o_md_ack_p30,    
        
        iv_md_p31,
        i_md_wr_p31,
        o_md_ack_p31,            
        
        iv_md_p32,
        i_md_wr_p32,
        o_md_ack_p32,
        
        o_tsmp_lookup_table_key_wr    ,
        ov_tsmp_lookup_table_key      ,
        iv_tsmp_lookup_table_outport  ,
        i_tsmp_lookup_table_outport_wr,
        
        ov_desp    ,
        o_desp_wr,

        ov_pkt_bufid      ,
        o_pkt_bufid_wr    ,
        ov_pkt_bufid_cnt  ,
        
        iv_addr           ,
        iv_wdata          ,
        i_wr              ,
        i_rd              ,
        
        o_wr              ,
        ov_addr           ,
        ov_rdata          
);

// I/O
// clk & rst
input                  i_clk;                   //125Mhz
input                  i_rst_n;

input                  i_cyclestart;
input      [10:0]      iv_inject_period;

input      [(NUM_XGMAC + NUM_GMAC + 1)  -1:0]         i_pkt_rx_finish   ;
//input                  i_pkt_rx_finish_p0   ;
//input                  i_pkt_rx_finish_p1   ;
//input                  i_pkt_rx_finish_p2   ;
//input                  i_pkt_rx_finish_p3   ;
//input                  i_pkt_rx_finish_p4   ;
//input                  i_pkt_rx_finish_p5   ;
//input                  i_pkt_rx_finish_p6   ;
//input                  i_pkt_rx_finish_p7   ;
//input                  i_pkt_rx_finish_p8   ;
//input                  i_pkt_rx_finish_p9   ;
//input                  i_pkt_rx_finish_p10  ;
//input                  i_pkt_rx_finish_p11  ;
//input                  i_pkt_rx_finish_p12  ;
//input                  i_pkt_rx_finish_p13  ;
//input                  i_pkt_rx_finish_p14  ;
//input                  i_pkt_rx_finish_p15  ;
//input                  i_pkt_rx_finish_p16  ;
//input                  i_pkt_rx_finish_p17  ;
//input                  i_pkt_rx_finish_p18  ;
//input                  i_pkt_rx_finish_p19  ;
//input                  i_pkt_rx_finish_p20  ;
//input                  i_pkt_rx_finish_p21  ;
//input                  i_pkt_rx_finish_p22  ;
//input                  i_pkt_rx_finish_p23  ;
//input                  i_pkt_rx_finish_p24  ;
//input                  i_pkt_rx_finish_p25  ;
//input                  i_pkt_rx_finish_p26  ;
//input                  i_pkt_rx_finish_p27  ;
//input                  i_pkt_rx_finish_p28  ;
//input                  i_pkt_rx_finish_p29  ;
//input                  i_pkt_rx_finish_p30  ;
//input                  i_pkt_rx_finish_p31  ;
//input                  i_pkt_rx_finish_p32  ;
// md from p0
input      [299:0]     iv_md_p0;
input                  i_md_wr_p0;
output                 o_md_ack_p0;
// md from p1      
input      [299:0]     iv_md_p1;
input                  i_md_wr_p1;
output                 o_md_ack_p1;
// md from p2      
input      [299:0]     iv_md_p2;
input                  i_md_wr_p2;
output                 o_md_ack_p2;
// md from p3      
input      [299:0]     iv_md_p3;
input                  i_md_wr_p3;
output                 o_md_ack_p3; 
        
input      [299:0]     iv_md_p4;
input                  i_md_wr_p4;
output                 o_md_ack_p4;    

input      [299:0]     iv_md_p5;
input                  i_md_wr_p5;
output                 o_md_ack_p5;    

input      [299:0]     iv_md_p6;
input                  i_md_wr_p6;
output                 o_md_ack_p6;    

input      [299:0]     iv_md_p7;
input                  i_md_wr_p7;
output                 o_md_ack_p7;    

input      [299:0]     iv_md_p8;
input                  i_md_wr_p8;
output                 o_md_ack_p8;    

input      [299:0]     iv_md_p9;
input                  i_md_wr_p9;
output                 o_md_ack_p9;    

input      [299:0]     iv_md_p10;
input                  i_md_wr_p10;
output                 o_md_ack_p10;    

input      [299:0]     iv_md_p11;
input                  i_md_wr_p11;
output                 o_md_ack_p11;    

input      [299:0]     iv_md_p12;
input                  i_md_wr_p12;
output                 o_md_ack_p12;    

input      [299:0]     iv_md_p13;
input                  i_md_wr_p13;
output                 o_md_ack_p13;    

input      [299:0]     iv_md_p14;
input                  i_md_wr_p14;
output                 o_md_ack_p14;    

input      [299:0]     iv_md_p15;
input                  i_md_wr_p15;
output                 o_md_ack_p15;    

input      [299:0]     iv_md_p16;
input                  i_md_wr_p16;
output                 o_md_ack_p16;    

input      [299:0]     iv_md_p17;
input                  i_md_wr_p17;
output                 o_md_ack_p17;    

input      [299:0]     iv_md_p18;
input                  i_md_wr_p18;
output                 o_md_ack_p18;    

input      [299:0]     iv_md_p19;
input                  i_md_wr_p19;
output                 o_md_ack_p19;    

input      [299:0]     iv_md_p20;
input                  i_md_wr_p20;
output                 o_md_ack_p20;    

input      [299:0]     iv_md_p21;
input                  i_md_wr_p21;
output                 o_md_ack_p21;    

input      [299:0]     iv_md_p22;
input                  i_md_wr_p22;
output                 o_md_ack_p22;    

input      [299:0]     iv_md_p23;
input                  i_md_wr_p23;
output                 o_md_ack_p23;    

input      [299:0]     iv_md_p24;
input                  i_md_wr_p24;
output                 o_md_ack_p24;    

input      [299:0]     iv_md_p25;
input                  i_md_wr_p25;
output                 o_md_ack_p25;    

input      [299:0]     iv_md_p26;
input                  i_md_wr_p26;
output                 o_md_ack_p26;    

input      [299:0]     iv_md_p27;
input                  i_md_wr_p27;
output                 o_md_ack_p27;    

input      [299:0]     iv_md_p28;
input                  i_md_wr_p28;
output                 o_md_ack_p28;    

input      [299:0]     iv_md_p29;
input                  i_md_wr_p29;
output                 o_md_ack_p29;    

input      [299:0]     iv_md_p30;
input                  i_md_wr_p30;
output                 o_md_ack_p30;    

input      [299:0]     iv_md_p31;
input                  i_md_wr_p31;
output                 o_md_ack_p31;            

input      [299:0]     iv_md_p32;
input                  i_md_wr_p32;
output                 o_md_ack_p32;
//tsmp lookup table
output                 o_tsmp_lookup_table_key_wr    ;
output     [47:0]      ov_tsmp_lookup_table_key      ;
input      [32:0]      iv_tsmp_lookup_table_outport  ;
input                  i_tsmp_lookup_table_outport_wr;
// 
output     [87:0]      ov_desp;
output                 o_desp_wr;
//forward cnt to pkt_centralize_bufm_memory
output     [8:0]       ov_pkt_bufid      ;
output                 o_pkt_bufid_wr    ;
output     [5:0]       ov_pkt_bufid_cnt  ;
//lookup table RAM
input      [18:0]      iv_addr           ;
input      [31:0]      iv_wdata          ;
input                  i_wr              ;
input                  i_rd              ;
               
output                 o_wr              ;
output     [18:0]      ov_addr           ;
output     [31:0]      ov_rdata          ;


 `ifdef  COUNT_ENABLE
(*MARK_DEBUG="true"*)reg [31:0]  ov_desp_count;
(*MARK_DEBUG="true"*)reg [15:0]  iv_md_p16_count;
(*MARK_DEBUG="true"*)reg [15:0]  iv_md_p17_count;
(*MARK_DEBUG="true"*)reg [15:0]  iv_md_p18_count;
(*MARK_DEBUG="true"*)reg [15:0]  iv_md_p19_count;
wire iv_md16_add;
wire iv_md17_add;
wire iv_md18_add;
wire iv_md19_add;
assign iv_md16_add = i_md_wr_p16&o_md_ack_p16;
assign iv_md17_add = i_md_wr_p17&o_md_ack_p17;
assign iv_md18_add = i_md_wr_p18&o_md_ack_p18;
assign iv_md19_add = i_md_wr_p19&o_md_ack_p19;
always @(posedge i_clk or negedge i_rst_n) 
if(~i_rst_n)    begin
   ov_desp_count  <=  32'b0;
   iv_md_p16_count <=  16'b0;
   iv_md_p17_count <=  16'b0;
   iv_md_p18_count <=  16'b0;
   iv_md_p19_count <=  16'b0;
end
else    begin
       if(o_desp_wr && (ov_desp[42:37] == 6'd19))begin    
           ov_desp_count  <=  ov_desp_count + 1'b1;
       end
       else begin
           ov_desp_count <= ov_desp_count;  
       end
       iv_md_p16_count <=  iv_md_p16_count + iv_md16_add;
       iv_md_p17_count <=  iv_md_p17_count + iv_md17_add;
       iv_md_p18_count <=  iv_md_p18_count + iv_md18_add;
       iv_md_p19_count <=  iv_md_p19_count + iv_md19_add;
end
`endif   

wire       [299:0]     wv_md_ica2fso     ;
wire                   w_md_wr_ica2fso   ;

wire       [5:0]       wv_dmacram_addr_cpe2ram    ;
wire       [81:0]      wv_dmacram_wdata_cpe2ram   ;
wire                   w_dmacram_wr_cpe2ram       ;
wire       [81:0]      wv_dmacram_rdata_ram2cpe   ;
wire                   w_dmacram_rd_cpe2ram       ;

wire    [2:0]       wv_ipram_addr_cpe2ram                   ;
wire    [64:0]      wv_ipram_wdata_cpe2ram                  ;
wire                w_ipram_wr_cpe2ram                      ;
wire                w_ipram_rd_cpe2ram                      ;
wire    [64:0]      wv_ipram_rdata_ram2cpe                  ;

wire    [31:0]      wv_droute_portbm_cpe2tlp                ;
wire    [31:0]      wv_sroute_portbm_cpe2tlp                ;
wire                w_unknown_multicast_forwardmode_cpe2tlp ;


wire       [13:0]      wv_flowidram_addr_cpe2ram  ;
wire       [73:0]      wv_flowidram_wdata_cpe2ram ;
wire                   w_flowidram_wr_cpe2ram     ;
wire       [73:0]      wv_flowidram_rdata_ram2cpe ;
wire                   w_flowidram_rd_cpe2ram     ;

wire       [5:0]       wv_fwdmoderam_addr_cpe2ram  ;
wire       [33:0]      wv_fwdmoderam_wdata_cpe2ram ;
wire                   w_fwdmoderam_wr_cpe2ram     ;
wire       [33:0]      wv_fwdmoderam_rdata_ram2cpe ;
wire                   w_fwdmoderam_rd_cpe2ram     ;

wire       [299:0]     wv_md_tlp2deg              ;
wire                   w_md_wr_tlp2deg            ;

wire       [87:0]      wv_descriptor_dge2fmc      ;
wire                   w_descriptor_wr_dge2fmc    ;

wire       [32:0]      wv_broadcast_storm_prevent_outport_cpe2tlp   ;

wire                   w_hit_cnt_clr_cpe2tlp       ;
                       
wire      [15:0]       wv_entry0_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry1_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry2_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry3_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry4_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry5_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry6_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry7_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry8_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry9_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry10_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry11_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry12_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry13_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry14_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry15_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry16_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry17_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry18_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry19_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry20_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry21_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry22_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry23_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry24_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry25_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry26_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry27_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry28_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry29_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry30_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry31_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry32_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry33_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry34_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry35_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry36_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry37_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry38_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry39_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry40_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry41_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry42_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry43_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry44_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry45_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry46_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry47_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry48_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry49_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry50_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry51_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry52_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry53_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry54_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry55_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry56_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry57_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry58_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry59_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry60_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry61_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry62_hit_cnt_tlp2cpe   ;
wire      [15:0]       wv_entry63_hit_cnt_tlp2cpe   ;

input_convergence_adaptation input_convergence_adaptation_inst(
.i_clk                          (i_clk  ),
.i_rst_n                        (i_rst_n),

.iv_md_p0                       (iv_md_p0   ),
.i_md_wr_p0                     (i_md_wr_p0 ),
.o_md_ack_p0                    (o_md_ack_p0),

.iv_md_p1                       (iv_md_p1   ),
.i_md_wr_p1                     (i_md_wr_p1 ),
.o_md_ack_p1                    (o_md_ack_p1),

.iv_md_p2                       (iv_md_p2   ),
.i_md_wr_p2                     (i_md_wr_p2 ),
.o_md_ack_p2                    (o_md_ack_p2),

.iv_md_p3                       (iv_md_p3   ),
.i_md_wr_p3                     (i_md_wr_p3 ),
.o_md_ack_p3                    (o_md_ack_p3),

.iv_md_p4                       (iv_md_p4       ),
.i_md_wr_p4                     (i_md_wr_p4     ),
.o_md_ack_p4                    (o_md_ack_p4    ),
 
.iv_md_p5                       (iv_md_p5       ),
.i_md_wr_p5                     (i_md_wr_p5     ),
.o_md_ack_p5                    (o_md_ack_p5    ),
 
.iv_md_p6                       (iv_md_p6       ),
.i_md_wr_p6                     (i_md_wr_p6     ),
.o_md_ack_p6                    (o_md_ack_p6    ),
 
.iv_md_p7                       (iv_md_p7       ),
.i_md_wr_p7                     (i_md_wr_p7     ),
.o_md_ack_p7                    (o_md_ack_p7    ),
 
.iv_md_p8                       (iv_md_p8       ),
.i_md_wr_p8                     (i_md_wr_p8     ),
.o_md_ack_p8                    (o_md_ack_p8    ),
 
.iv_md_p9                       (iv_md_p9       ),
.i_md_wr_p9                     (i_md_wr_p9     ),
.o_md_ack_p9                    (o_md_ack_p9    ),
 
.iv_md_p10                      (iv_md_p10      ),
.i_md_wr_p10                    (i_md_wr_p10    ),
.o_md_ack_p10                   (o_md_ack_p10   ),
 
.iv_md_p11                      (iv_md_p11      ),
.i_md_wr_p11                    (i_md_wr_p11    ),
.o_md_ack_p11                   (o_md_ack_p11   ),
 
.iv_md_p12                      (iv_md_p12      ),
.i_md_wr_p12                    (i_md_wr_p12    ),
.o_md_ack_p12                   (o_md_ack_p12   ),
 
.iv_md_p13                      (iv_md_p13      ),
.i_md_wr_p13                    (i_md_wr_p13    ),
.o_md_ack_p13                   (o_md_ack_p13   ),
 
.iv_md_p14                      (iv_md_p14      ),
.i_md_wr_p14                    (i_md_wr_p14    ),
.o_md_ack_p14                   (o_md_ack_p14   ),
 
.iv_md_p15                      (iv_md_p15      ),
.i_md_wr_p15                    (i_md_wr_p15    ),
.o_md_ack_p15                   (o_md_ack_p15   ),
 
.iv_md_p16                      (iv_md_p16      ),
.i_md_wr_p16                    (i_md_wr_p16    ),
.o_md_ack_p16                   (o_md_ack_p16   ),
 
.iv_md_p17                      (iv_md_p17      ),
.i_md_wr_p17                    (i_md_wr_p17    ),
.o_md_ack_p17                   (o_md_ack_p17   ),
 
.iv_md_p18                      (iv_md_p18      ),
.i_md_wr_p18                    (i_md_wr_p18    ),
.o_md_ack_p18                   (o_md_ack_p18   ),
 
.iv_md_p19                      (iv_md_p19      ),
.i_md_wr_p19                    (i_md_wr_p19    ),
.o_md_ack_p19                   (o_md_ack_p19   ),
 
.iv_md_p20                      (iv_md_p20      ),
.i_md_wr_p20                    (i_md_wr_p20    ),
.o_md_ack_p20                   (o_md_ack_p20   ),
 
.iv_md_p21                      (iv_md_p21      ),
.i_md_wr_p21                    (i_md_wr_p21    ),
.o_md_ack_p21                   (o_md_ack_p21   ),
 
.iv_md_p22                      (iv_md_p22      ),
.i_md_wr_p22                    (i_md_wr_p22    ),
.o_md_ack_p22                   (o_md_ack_p22   ),
 
.iv_md_p23                      (iv_md_p23      ),
.i_md_wr_p23                    (i_md_wr_p23    ),
.o_md_ack_p23                   (o_md_ack_p23   ),
 
.iv_md_p24                      (iv_md_p24      ),
.i_md_wr_p24                    (i_md_wr_p24    ),
.o_md_ack_p24                   (o_md_ack_p24   ),
 
.iv_md_p25                      (iv_md_p25      ),
.i_md_wr_p25                    (i_md_wr_p25    ),
.o_md_ack_p25                   (o_md_ack_p25   ),
 
.iv_md_p26                      (iv_md_p26      ),
.i_md_wr_p26                    (i_md_wr_p26    ),
.o_md_ack_p26                   (o_md_ack_p26   ),
 
.iv_md_p27                      (iv_md_p27      ),
.i_md_wr_p27                    (i_md_wr_p27    ),
.o_md_ack_p27                   (o_md_ack_p27   ),
 
.iv_md_p28                      (iv_md_p28      ),
.i_md_wr_p28                    (i_md_wr_p28    ),
.o_md_ack_p28                   (o_md_ack_p28   ),
 
.iv_md_p29                      (iv_md_p29      ),
.i_md_wr_p29                    (i_md_wr_p29    ),
.o_md_ack_p29                   (o_md_ack_p29   ),
 
.iv_md_p30                      (iv_md_p30      ),
.i_md_wr_p30                    (i_md_wr_p30    ),
.o_md_ack_p30                   (o_md_ack_p30   ),
 
.iv_md_p31                      (iv_md_p31      ),
.i_md_wr_p31                    (i_md_wr_p31    ),
.o_md_ack_p31                   (o_md_ack_p31   ),
 
.iv_md_p32                      (iv_md_p32      ),
.i_md_wr_p32                    (i_md_wr_p32    ),
.o_md_ack_p32                   (o_md_ack_p32   ),

.ov_md                          (wv_md_ica2fso   ),
.o_md_wr                        (w_md_wr_ica2fso )

);
table_lookup_pipeline table_lookup_pipeline_inst(
.i_clk                          (i_clk  ),
.i_rst_n                        (i_rst_n),

.i_cyclestart                  (i_cyclestart),
.iv_inject_period               (iv_inject_period),
                                
.iv_md                          (wv_md_ica2fso  ),
.i_md_wr                        (w_md_wr_ica2fso),
                                
.iv_dmacram_addr                (wv_dmacram_addr_cpe2ram     ),
.iv_dmacram_wdata               (wv_dmacram_wdata_cpe2ram    ),
.i_dmacram_wr                   (w_dmacram_wr_cpe2ram        ),
.ov_dmacram_rdata               (wv_dmacram_rdata_ram2cpe    ),
.i_dmacram_rd                   (w_dmacram_rd_cpe2ram        ),

.iv_ipram_addr_cpe2ram                  (wv_ipram_addr_cpe2ram ),
.iv_ipram_wdata_cpe2ram                 (wv_ipram_wdata_cpe2ram),
.i_ipram_wr_cpe2ram                     (w_ipram_wr_cpe2ram    ),
.i_ipram_rd_cpe2ram                     (w_ipram_rd_cpe2ram    ),
.ov_ipram_rdata_ram2cpe                 (wv_ipram_rdata_ram2cpe),

.iv_droute_portbm_cpe2tlp               (wv_droute_portbm_cpe2tlp               ),
.iv_sroute_portbm_cpe2tlp               (wv_sroute_portbm_cpe2tlp               ),
.i_unknown_multicast_forwardmode_cpe2tlp(w_unknown_multicast_forwardmode_cpe2tlp),
                                
.iv_flowidram_addr              (wv_flowidram_addr_cpe2ram   ),
.iv_flowidram_wdata             (wv_flowidram_wdata_cpe2ram  ),
.i_flowidram_wr                 (w_flowidram_wr_cpe2ram      ),
.ov_flowidram_rdata             (wv_flowidram_rdata_ram2cpe  ),
.i_flowidram_rd                 (w_flowidram_rd_cpe2ram      ),

.o_tsmp_lookup_table_key_wr     (o_tsmp_lookup_table_key_wr    ),
.ov_tsmp_lookup_table_key       (ov_tsmp_lookup_table_key      ),
.iv_tsmp_lookup_table_outport   (iv_tsmp_lookup_table_outport  ),
.i_tsmp_lookup_table_outport_wr (i_tsmp_lookup_table_outport_wr),

.ov_md                          (wv_md_tlp2deg                 ),
.o_md_wr                        (w_md_wr_tlp2deg               ),

.iv_broadcast_storm_prevent_outport      (wv_broadcast_storm_prevent_outport_cpe2tlp),

.i_hit_cnt_clr                   (w_hit_cnt_clr_cpe2tlp    ), 
               
.ov_entry0_hit_cnt               (wv_entry0_hit_cnt_tlp2cpe),
.ov_entry1_hit_cnt               (wv_entry1_hit_cnt_tlp2cpe),
.ov_entry2_hit_cnt               (wv_entry2_hit_cnt_tlp2cpe),
.ov_entry3_hit_cnt               (wv_entry3_hit_cnt_tlp2cpe),
.ov_entry4_hit_cnt               (wv_entry4_hit_cnt_tlp2cpe),
.ov_entry5_hit_cnt               (wv_entry5_hit_cnt_tlp2cpe),
.ov_entry6_hit_cnt               (wv_entry6_hit_cnt_tlp2cpe),
.ov_entry7_hit_cnt               (wv_entry7_hit_cnt_tlp2cpe),
.ov_entry8_hit_cnt              (wv_entry8_hit_cnt_tlp2cpe ),
.ov_entry9_hit_cnt              (wv_entry9_hit_cnt_tlp2cpe ),
.ov_entry10_hit_cnt             (wv_entry10_hit_cnt_tlp2cpe),
.ov_entry11_hit_cnt             (wv_entry11_hit_cnt_tlp2cpe),
.ov_entry12_hit_cnt             (wv_entry12_hit_cnt_tlp2cpe),
.ov_entry13_hit_cnt             (wv_entry13_hit_cnt_tlp2cpe),
.ov_entry14_hit_cnt             (wv_entry14_hit_cnt_tlp2cpe),
.ov_entry15_hit_cnt             (wv_entry15_hit_cnt_tlp2cpe),         
.ov_entry16_hit_cnt             (wv_entry16_hit_cnt_tlp2cpe),
.ov_entry17_hit_cnt             (wv_entry17_hit_cnt_tlp2cpe),
.ov_entry18_hit_cnt             (wv_entry18_hit_cnt_tlp2cpe),
.ov_entry19_hit_cnt             (wv_entry19_hit_cnt_tlp2cpe),
.ov_entry20_hit_cnt             (wv_entry20_hit_cnt_tlp2cpe),
.ov_entry21_hit_cnt             (wv_entry21_hit_cnt_tlp2cpe),
.ov_entry22_hit_cnt             (wv_entry22_hit_cnt_tlp2cpe),
.ov_entry23_hit_cnt             (wv_entry23_hit_cnt_tlp2cpe),         
.ov_entry24_hit_cnt             (wv_entry24_hit_cnt_tlp2cpe),
.ov_entry25_hit_cnt             (wv_entry25_hit_cnt_tlp2cpe),
.ov_entry26_hit_cnt             (wv_entry26_hit_cnt_tlp2cpe),
.ov_entry27_hit_cnt             (wv_entry27_hit_cnt_tlp2cpe),
.ov_entry28_hit_cnt             (wv_entry28_hit_cnt_tlp2cpe),
.ov_entry29_hit_cnt             (wv_entry29_hit_cnt_tlp2cpe),
.ov_entry30_hit_cnt             (wv_entry30_hit_cnt_tlp2cpe),
.ov_entry31_hit_cnt             (wv_entry31_hit_cnt_tlp2cpe),         
.ov_entry32_hit_cnt             (wv_entry32_hit_cnt_tlp2cpe),
.ov_entry33_hit_cnt             (wv_entry33_hit_cnt_tlp2cpe),
.ov_entry34_hit_cnt             (wv_entry34_hit_cnt_tlp2cpe),
.ov_entry35_hit_cnt             (wv_entry35_hit_cnt_tlp2cpe),
.ov_entry36_hit_cnt             (wv_entry36_hit_cnt_tlp2cpe),
.ov_entry37_hit_cnt             (wv_entry37_hit_cnt_tlp2cpe),
.ov_entry38_hit_cnt             (wv_entry38_hit_cnt_tlp2cpe),
.ov_entry39_hit_cnt             (wv_entry39_hit_cnt_tlp2cpe),         
.ov_entry40_hit_cnt             (wv_entry40_hit_cnt_tlp2cpe),
.ov_entry41_hit_cnt             (wv_entry41_hit_cnt_tlp2cpe),
.ov_entry42_hit_cnt             (wv_entry42_hit_cnt_tlp2cpe),
.ov_entry43_hit_cnt             (wv_entry43_hit_cnt_tlp2cpe),
.ov_entry44_hit_cnt             (wv_entry44_hit_cnt_tlp2cpe),
.ov_entry45_hit_cnt             (wv_entry45_hit_cnt_tlp2cpe),
.ov_entry46_hit_cnt             (wv_entry46_hit_cnt_tlp2cpe),
.ov_entry47_hit_cnt             (wv_entry47_hit_cnt_tlp2cpe),         
.ov_entry48_hit_cnt             (wv_entry48_hit_cnt_tlp2cpe),
.ov_entry49_hit_cnt             (wv_entry49_hit_cnt_tlp2cpe),
.ov_entry50_hit_cnt             (wv_entry50_hit_cnt_tlp2cpe),
.ov_entry51_hit_cnt             (wv_entry51_hit_cnt_tlp2cpe),
.ov_entry52_hit_cnt             (wv_entry52_hit_cnt_tlp2cpe),
.ov_entry53_hit_cnt             (wv_entry53_hit_cnt_tlp2cpe),
.ov_entry54_hit_cnt             (wv_entry54_hit_cnt_tlp2cpe),
.ov_entry55_hit_cnt             (wv_entry55_hit_cnt_tlp2cpe),         
.ov_entry56_hit_cnt             (wv_entry56_hit_cnt_tlp2cpe),
.ov_entry57_hit_cnt             (wv_entry57_hit_cnt_tlp2cpe),
.ov_entry58_hit_cnt             (wv_entry58_hit_cnt_tlp2cpe),
.ov_entry59_hit_cnt             (wv_entry59_hit_cnt_tlp2cpe),
.ov_entry60_hit_cnt             (wv_entry60_hit_cnt_tlp2cpe),
.ov_entry61_hit_cnt             (wv_entry61_hit_cnt_tlp2cpe),
.ov_entry62_hit_cnt             (wv_entry62_hit_cnt_tlp2cpe),
.ov_entry63_hit_cnt             (wv_entry63_hit_cnt_tlp2cpe)
);


descriptor_generate descriptor_generate_inst(
.i_clk                    (i_clk             ),
.i_rst_n                  (i_rst_n           ),
                          
.iv_md                    (wv_md_tlp2deg     ),
.i_md_wr                  (w_md_wr_tlp2deg   ),
                          
.ov_pkt_bufid             (ov_pkt_bufid        ),
.o_pkt_bufid_wr           (o_pkt_bufid_wr      ),
.ov_pkt_bufid_cnt 	      (ov_pkt_bufid_cnt    ),

.ov_descriptor            (wv_descriptor_dge2fmc   ),
.o_descriptor_wr          (w_descriptor_wr_dge2fmc )

);

forward_mode_control 
#(
    .NUM_GMAC(NUM_GMAC)
   ,.NUM_XGMAC(NUM_XGMAC)
)
forward_mode_control_inst
(
.i_clk                 (i_clk              ),   
.i_rst_n               (i_rst_n            ),
  
.i_pkt_rx_finish       (i_pkt_rx_finish),  
//.i_pkt_rx_finish_p0    (i_pkt_rx_finish_p0 ),
//.i_pkt_rx_finish_p1    (i_pkt_rx_finish_p1 ),
//.i_pkt_rx_finish_p2    (i_pkt_rx_finish_p2 ),
//.i_pkt_rx_finish_p3    (i_pkt_rx_finish_p3 ),
//.i_pkt_rx_finish_p4    (i_pkt_rx_finish_p4 ),
//.i_pkt_rx_finish_p5    (i_pkt_rx_finish_p5 ),
//.i_pkt_rx_finish_p6    (i_pkt_rx_finish_p6 ),
//.i_pkt_rx_finish_p7    (i_pkt_rx_finish_p7 ),
//.i_pkt_rx_finish_p8    (i_pkt_rx_finish_p8 ),
//.i_pkt_rx_finish_p9    (i_pkt_rx_finish_p9 ),
//.i_pkt_rx_finish_p10   (i_pkt_rx_finish_p10),
//.i_pkt_rx_finish_p11   (i_pkt_rx_finish_p11),
//.i_pkt_rx_finish_p12   (i_pkt_rx_finish_p12),
//.i_pkt_rx_finish_p13   (i_pkt_rx_finish_p13),
//.i_pkt_rx_finish_p14   (i_pkt_rx_finish_p14),
//.i_pkt_rx_finish_p15   (i_pkt_rx_finish_p15),
//.i_pkt_rx_finish_p16   (i_pkt_rx_finish_p16),
//.i_pkt_rx_finish_p17   (i_pkt_rx_finish_p17),
//.i_pkt_rx_finish_p18   (i_pkt_rx_finish_p18),
//.i_pkt_rx_finish_p19   (i_pkt_rx_finish_p19),
//.i_pkt_rx_finish_p20   (i_pkt_rx_finish_p20),
//.i_pkt_rx_finish_p21   (i_pkt_rx_finish_p21),
//.i_pkt_rx_finish_p22   (i_pkt_rx_finish_p22),
//.i_pkt_rx_finish_p23   (i_pkt_rx_finish_p23),
//.i_pkt_rx_finish_p24   (i_pkt_rx_finish_p24),
//.i_pkt_rx_finish_p25   (i_pkt_rx_finish_p25),
//.i_pkt_rx_finish_p26   (i_pkt_rx_finish_p26),
//.i_pkt_rx_finish_p27   (i_pkt_rx_finish_p27),
//.i_pkt_rx_finish_p28   (i_pkt_rx_finish_p28),
//.i_pkt_rx_finish_p29   (i_pkt_rx_finish_p29),
//.i_pkt_rx_finish_p30   (i_pkt_rx_finish_p30),
//.i_pkt_rx_finish_p31   (i_pkt_rx_finish_p31),
//.i_pkt_rx_finish_p32   (i_pkt_rx_finish_p32),
                        
.iv_desp               (wv_descriptor_dge2fmc            ),
.i_desp_wr             (w_descriptor_wr_dge2fmc          ),	
                        
.iv_fwdmoderam_addr    (wv_fwdmoderam_addr_cpe2ram ),
.iv_fwdmoderam_wdata   (wv_fwdmoderam_wdata_cpe2ram),
.i_fwdmoderam_wr       (w_fwdmoderam_wr_cpe2ram    ),
.ov_fwdmoderam_rdata   (wv_fwdmoderam_rdata_ram2cpe),
.i_fwdmoderam_rd       (w_fwdmoderam_rd_cpe2ram    ),
                        
.ov_desp               (ov_desp            ), 
.o_desp_wr             (o_desp_wr          )
         
);
command_parse_and_encapsulate_clt command_parse_and_encapsulate_clt_inst(
.i_clk                       (i_clk              ),       
.i_rst_n                     (i_rst_n            ),      

.iv_addr                     (iv_addr            ),         
.iv_wdata                    (iv_wdata           ),         
.i_wr                        (i_wr               ),      
.i_rd                        (i_rd               ),        

.o_wr                        (o_wr               ),      
.ov_addr                     (ov_addr            ),      
.ov_rdata                    (ov_rdata           ),      

.ov_flowidram_addr           (wv_flowidram_addr_cpe2ram  ),      
.ov_flowidram_wdata          (wv_flowidram_wdata_cpe2ram ),      
.o_flowidram_wr              (w_flowidram_wr_cpe2ram     ),      
.iv_flowidram_rdata          (wv_flowidram_rdata_ram2cpe ),      
.o_flowidram_rd              (w_flowidram_rd_cpe2ram     ),

.ov_dmacram_addr             (wv_dmacram_addr_cpe2ram    ),
.ov_dmacram_wdata            (wv_dmacram_wdata_cpe2ram   ),
.o_dmacram_wr                (w_dmacram_wr_cpe2ram       ),
.iv_dmacram_rdata            (wv_dmacram_rdata_ram2cpe   ),
.o_dmacram_rd                (w_dmacram_rd_cpe2ram       ),

.ov_ipram_addr_cpe2ram                   (wv_ipram_addr_cpe2ram ),
.ov_ipram_wdata_cpe2ram                  (wv_ipram_wdata_cpe2ram),
.o_ipram_wr_cpe2ram                      (w_ipram_wr_cpe2ram    ),
.o_ipram_rd_cpe2ram                      (w_ipram_rd_cpe2ram    ),
.iv_ipram_rdata_ram2cpe                  (wv_ipram_rdata_ram2cpe),

.ov_droute_portbm_cpe2tlp                (wv_droute_portbm_cpe2tlp               ),
.ov_sroute_portbm_cpe2tlp                (wv_sroute_portbm_cpe2tlp               ),
.o_unknown_multicast_forwardmode_cpe2tlp (w_unknown_multicast_forwardmode_cpe2tlp),


.ov_fwdmoderam_addr          (wv_fwdmoderam_addr_cpe2ram   ),
.ov_fwdmoderam_wdata         (wv_fwdmoderam_wdata_cpe2ram  ),
.o_fwdmoderam_wr             (w_fwdmoderam_wr_cpe2ram      ),
.iv_fwdmoderam_rdata         (wv_fwdmoderam_rdata_ram2cpe  ),
.o_fwdmoderam_rd             (w_fwdmoderam_rd_cpe2ram      ),  

.ov_broadcast_storm_prevent_outport   (wv_broadcast_storm_prevent_outport_cpe2tlp  ),

.o_hit_cnt_clr               (w_hit_cnt_clr_cpe2tlp      ), 
                                                         
.iv_entry0_hit_cnt           (wv_entry0_hit_cnt_tlp2cpe  ),
.iv_entry1_hit_cnt           (wv_entry1_hit_cnt_tlp2cpe  ),
.iv_entry2_hit_cnt           (wv_entry2_hit_cnt_tlp2cpe  ),
.iv_entry3_hit_cnt           (wv_entry3_hit_cnt_tlp2cpe  ),
.iv_entry4_hit_cnt           (wv_entry4_hit_cnt_tlp2cpe  ),
.iv_entry5_hit_cnt           (wv_entry5_hit_cnt_tlp2cpe  ),
.iv_entry6_hit_cnt           (wv_entry6_hit_cnt_tlp2cpe  ),
.iv_entry7_hit_cnt           (wv_entry7_hit_cnt_tlp2cpe  ),
.iv_entry8_hit_cnt           (wv_entry8_hit_cnt_tlp2cpe ),
.iv_entry9_hit_cnt           (wv_entry9_hit_cnt_tlp2cpe ),
.iv_entry10_hit_cnt          (wv_entry10_hit_cnt_tlp2cpe),
.iv_entry11_hit_cnt          (wv_entry11_hit_cnt_tlp2cpe),
.iv_entry12_hit_cnt          (wv_entry12_hit_cnt_tlp2cpe),
.iv_entry13_hit_cnt          (wv_entry13_hit_cnt_tlp2cpe),
.iv_entry14_hit_cnt          (wv_entry14_hit_cnt_tlp2cpe),
.iv_entry15_hit_cnt          (wv_entry15_hit_cnt_tlp2cpe),         
.iv_entry16_hit_cnt          (wv_entry16_hit_cnt_tlp2cpe),
.iv_entry17_hit_cnt          (wv_entry17_hit_cnt_tlp2cpe),
.iv_entry18_hit_cnt          (wv_entry18_hit_cnt_tlp2cpe),
.iv_entry19_hit_cnt          (wv_entry19_hit_cnt_tlp2cpe),
.iv_entry20_hit_cnt          (wv_entry20_hit_cnt_tlp2cpe),
.iv_entry21_hit_cnt          (wv_entry21_hit_cnt_tlp2cpe),
.iv_entry22_hit_cnt          (wv_entry22_hit_cnt_tlp2cpe),
.iv_entry23_hit_cnt          (wv_entry23_hit_cnt_tlp2cpe),         
.iv_entry24_hit_cnt          (wv_entry24_hit_cnt_tlp2cpe),
.iv_entry25_hit_cnt          (wv_entry25_hit_cnt_tlp2cpe),
.iv_entry26_hit_cnt          (wv_entry26_hit_cnt_tlp2cpe),
.iv_entry27_hit_cnt          (wv_entry27_hit_cnt_tlp2cpe),
.iv_entry28_hit_cnt          (wv_entry28_hit_cnt_tlp2cpe),
.iv_entry29_hit_cnt          (wv_entry29_hit_cnt_tlp2cpe),
.iv_entry30_hit_cnt          (wv_entry30_hit_cnt_tlp2cpe),
.iv_entry31_hit_cnt          (wv_entry31_hit_cnt_tlp2cpe),         
.iv_entry32_hit_cnt          (wv_entry32_hit_cnt_tlp2cpe),
.iv_entry33_hit_cnt          (wv_entry33_hit_cnt_tlp2cpe),
.iv_entry34_hit_cnt          (wv_entry34_hit_cnt_tlp2cpe),
.iv_entry35_hit_cnt          (wv_entry35_hit_cnt_tlp2cpe),
.iv_entry36_hit_cnt          (wv_entry36_hit_cnt_tlp2cpe),
.iv_entry37_hit_cnt          (wv_entry37_hit_cnt_tlp2cpe),
.iv_entry38_hit_cnt          (wv_entry38_hit_cnt_tlp2cpe),
.iv_entry39_hit_cnt          (wv_entry39_hit_cnt_tlp2cpe),         
.iv_entry40_hit_cnt          (wv_entry40_hit_cnt_tlp2cpe),
.iv_entry41_hit_cnt          (wv_entry41_hit_cnt_tlp2cpe),
.iv_entry42_hit_cnt          (wv_entry42_hit_cnt_tlp2cpe),
.iv_entry43_hit_cnt          (wv_entry43_hit_cnt_tlp2cpe),
.iv_entry44_hit_cnt          (wv_entry44_hit_cnt_tlp2cpe),
.iv_entry45_hit_cnt          (wv_entry45_hit_cnt_tlp2cpe),
.iv_entry46_hit_cnt          (wv_entry46_hit_cnt_tlp2cpe),
.iv_entry47_hit_cnt          (wv_entry47_hit_cnt_tlp2cpe),         
.iv_entry48_hit_cnt          (wv_entry48_hit_cnt_tlp2cpe),
.iv_entry49_hit_cnt          (wv_entry49_hit_cnt_tlp2cpe),
.iv_entry50_hit_cnt          (wv_entry50_hit_cnt_tlp2cpe),
.iv_entry51_hit_cnt          (wv_entry51_hit_cnt_tlp2cpe),
.iv_entry52_hit_cnt          (wv_entry52_hit_cnt_tlp2cpe),
.iv_entry53_hit_cnt          (wv_entry53_hit_cnt_tlp2cpe),
.iv_entry54_hit_cnt          (wv_entry54_hit_cnt_tlp2cpe),
.iv_entry55_hit_cnt          (wv_entry55_hit_cnt_tlp2cpe),         
.iv_entry56_hit_cnt          (wv_entry56_hit_cnt_tlp2cpe),
.iv_entry57_hit_cnt          (wv_entry57_hit_cnt_tlp2cpe),
.iv_entry58_hit_cnt          (wv_entry58_hit_cnt_tlp2cpe),
.iv_entry59_hit_cnt          (wv_entry59_hit_cnt_tlp2cpe),
.iv_entry60_hit_cnt          (wv_entry60_hit_cnt_tlp2cpe),
.iv_entry61_hit_cnt          (wv_entry61_hit_cnt_tlp2cpe),
.iv_entry62_hit_cnt          (wv_entry62_hit_cnt_tlp2cpe),
.iv_entry63_hit_cnt          (wv_entry63_hit_cnt_tlp2cpe) 
);  



reg   [31:0] rv_p0_desp_rx_cnt;
reg   [31:0] rv_p1_desp_rx_cnt;
reg   [31:0] rv_p2_desp_rx_cnt;
reg   [31:0] rv_p3_desp_rx_cnt;
reg   [31:0] rv_p32_desp_rx_cnt;
reg   [31:0] rv_desp_tx_cnt;
always @(posedge i_clk or negedge i_rst_n) begin
    if(i_rst_n == 1'b0)begin
        rv_p0_desp_rx_cnt <= 32'b0;
        rv_p1_desp_rx_cnt <= 32'b0;
        rv_p2_desp_rx_cnt <= 32'b0;
        rv_p3_desp_rx_cnt <= 32'b0;
        rv_p32_desp_rx_cnt<= 32'b0;
        rv_desp_tx_cnt    <= 32'b0;
    end
    else begin 
        if(o_md_ack_p0)begin
            rv_p0_desp_rx_cnt <= rv_p0_desp_rx_cnt + 1'b1;
        end
        else begin
            rv_p0_desp_rx_cnt <= rv_p0_desp_rx_cnt;
        end
        
        if(o_md_ack_p1)begin
            rv_p1_desp_rx_cnt <= rv_p1_desp_rx_cnt + 1'b1;
        end
        else begin
            rv_p1_desp_rx_cnt <= rv_p1_desp_rx_cnt;
        end
        
        if(o_md_ack_p2)begin
            rv_p2_desp_rx_cnt <= rv_p2_desp_rx_cnt + 1'b1;
        end
        else begin
            rv_p2_desp_rx_cnt <= rv_p2_desp_rx_cnt;
        end

        if(o_md_ack_p3)begin
            rv_p3_desp_rx_cnt <= rv_p3_desp_rx_cnt + 1'b1;
        end
        else begin
            rv_p3_desp_rx_cnt <= rv_p3_desp_rx_cnt;
        end
        
        if(o_md_ack_p32)begin
            rv_p32_desp_rx_cnt <= rv_p32_desp_rx_cnt + 1'b1;
        end
        else begin
            rv_p32_desp_rx_cnt <= rv_p32_desp_rx_cnt;
        end        

        if(o_desp_wr)begin
            rv_desp_tx_cnt <= rv_desp_tx_cnt + 1'b1;
        end
        else begin
            rv_desp_tx_cnt <= rv_desp_tx_cnt;
        end      
    end
end 
endmodule
